When one thinks of leading-edge semiconductor companies, companies such as Intel, AMD, and Samsung instantly come to mind. But as more semiconductor companies emphasize IP and outsource their manufacturing, semiconductor foundries are playing a more important role in helping bring innovative technologies into the real world.
One major semiconductor foundry, Taiwan-based foundry Taiwan Semiconductor Manufacturing Company (TSMC) recently staged at its 2023 North America Technology Symposium in Santa Clara, CA, to show its work on various process and packaging technologies. The technologies address key markets such as automotive and high-speed computing,and include next-generation packaging such aschiplets and stacked chips.
TSMC has broadened its portfolio of 3nm processes. For instance, N3P, scheduled to enter production in the second half of 2024, offers an additional boost to N3E with 5% more speed at the same leakage, 5-10% power reduction at the same speed, and 1.04X more chip density.
Another process, N3X, is tailored for high performance computing (HPC) applications. N3X, which prioritizes performance and maximum clock frequencies, provides 5% more speed versus N3P at drive voltage of 1.2V, with the same improved chip density as N3P, and will enter volume production in 2025.
A third process, N3AE, or “Auto Early”, available in 2023, offers automotive process design kits (PDKs) based on N3E, and allows customers to launch designs on the 3nm node for automotive applications, leading to the fully automotive-qualified N3A process in 2025.
2mm On the Way
TSMC is also making progress on 2nm process technology, in both yield and device performance, and is on track to being production in 2025. The 2mm process will provide up to 15% speed improvement over N3E at the same power, and up to 30% power reduction at the same speed, and greater than 1.15X chip density.
Pushing the Limits of CMOS RF Technology with N4PRF – Beyond the N6RF technology announced in 2021, TSMC is developing N4PRF, an advanced CMOS radio frequency technology for digital-intensive RF applications such as WiFi 7 RF system-on-chip. N4PRF will support 1.77X greater logic density and 45% less logic power at the same speed compared with N6RF.
TSMC has also announced developments in its 3DFabric system integration technologies. TSMC is supporting the demands of HPC applications to fit more processors and memory in a single package through its Chip on Wafer on Substrate (CoWoS) solution. The CoWoS uses an up to six times reticle-size (~5,000mm2 ) RDL interposer, capable of accommodating 12 stacks of HBM memory.
In 3D chip stacking, TSMC announced SoIC-P, microbump versions of its System on Integrated Chips (SoIC) solutions providing a cost-effective way for 3D chip stacking. SoIC-P complements TSMC’s existing bumpless solutions for high-performance computing (HPC) applications, which are now known as SoIC-X.
For design support, TSMC introduced 3Dblox™ 1.5, the newest version of its open standard design language to lower the barriers to 3D IC design. 3Dblox™ 1.5 adds automated bump synthesis, helping designers deal with the complexities of large dies with thousands of bumps and potentially reducing design times by months.
TSMC also highlighted some of the technologies of its startup customer partners at the Technology Symposium. Some companies include: Achronix Semiconductor, a supplier of FPGAs; Ambq, which supplies SoC solutions for AI and other data-driven applications; InSilixia, a provider of technologies for medical applications; EdgeQ, which supplies a 5G Base Station on a chip; and Kinara, a supplier of AI inference processors.
Spencer Chin is a Senior Editor for Design News covering the electronics beat. He has many years of experience covering developments in components, semiconductors, subsystems, power, and other facets of electronics from both a business/supply-chain and technology perspective. He can be reached at [email protected]